1. Technical Field
The present invention generally relates to integrated circuit processing, and more particularly to methods relating to integrated circuit rework processes on semiconductor wafers
2. Related Art
Currently, integrated circuit BEOL (back end of the line) semiconductor processing rework processes are used for both ASIC (Application Specific Integrated Circuit) design and normal production. These rework processes have been developed for both and copper multi-level-metal wiring and are generally employed to correct yield or problems or a photomask error. Such rework processes enable QTAT (quicker turn around time) design verification and save integrated circuit fabrication costs. An example of a process is given in U.S. Pat. No. 6,332,988, the complete disclosure of which is incorporated by reference, wherein a process for reworking electroplated solder bump is disclosed.
The introduction of copper and low dielectric (k) technologies presents the for additional rework process definition because the physical and chemical properties low k dielectric materials differ significantly from silicon dioxide, and therefore are not to the same rework procedures. Such rework processes must integrate with POR (process of record) BEOL processing sequences, maintain planarity throughout rework process, remove multiple thin films including Si3N4, low k organic dielectrics, copper, liner materials, and stop on the top of the dielectric and tungsten interconnect region residing the electronically active devices such as transistors (typically called the front end). This dielectric is typically Boron-doped SiO2 or “BPSG” (Boron Phosphorous Silicate Glass), an electrical conductor fabricated of tungsten damascene is typically utilized so this can be abbreviated “BPSG/W.” Some conventional processes teach methods for a defective SiLK® layer caused by improper coating such as for a photoresist process. However, these conventional processes do not address rework of the final metal in addition to the dielectric BEOL.
Additionally, as integrated circuit device dimensions shrink with each successive the pitch at the lower wiring levels becomes challenging with respect to overlay shorting, via resistance of copper to copper vias in low k materials, line to metal line capacitance, and metal level to metal level cooling issues.
Therefore, there is a need for an integrated circuit rework process which results in vertical space between any or all BEOL levels, and which would be instrumental in facilitating removal and reconstruction of defective BEOL levels and in securing desired process latitude with respect to overlay, via resistance, line capacitance, and cooling.